From one to several instructions per cycle
Multi-pipeline superscalar processors

In the article [H 1 004] "Processors: pipelined instruction execution", we considered what are generally referred to as "scalar" processors. For these processors, pipelined instruction execution aims to achieve, in the ideal case, an execution rate of one instruction per clock cycle, since only one instruction can start at each clock cycle.

Increasing instruction throughput involves exploiting the instruction parallelism that exists in sequential programs, i.e. extracting from a sequence of sequential instructions those that...