Multi-pipeline or "restricted data flow" superscalars
Multi-pipeline superscalar processors

The multi-pipeline approach makes it possible to execute several instructions per cycle by breaking down pipelines into two parts: the first acquires n instructions simultaneously, decodes them, examines structural hazards (lack of hardware operators) and data dependencies, and constitutes the group of instructions that can start in the same clock cycle by dividing up into the various execution pipelines (integers, floats, memory accesses, etc.). Variations concern the number of instructions acquired per cycle (2 or 4) and the size of the groups, which can vary from 2 to 7 in the examples cited in this article.

Whatever the variants, the number of instructions that can be launched in one clock cycle is limited, and they are close together in the sequential flow of instructions. Newer instructions may be executable, while older instructions are waiting for available...