EMC, IS and IP simulation of our circuit case study
Méthodologie pour simuler et modéliser une carte électronique en CEM et intégrité du signal

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EMC, IS and IP simulation of our circuit case study
Méthodologie pour simuler et modéliser une carte électronique en CEM et intégrité du signal

Authors : Blaise RAVELO, Sébastien LALLÉCHÈRE

Review date: February 29, 2024 | Lire en français

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5. EMC, IS and IP simulation of our circuit case study

This section presents the simulation results for the circuit shown in figure 4 . As established in the previous section, the EMC analysis is based on consideration of the variabilities of the parameters at the origin of the aggression signals. Then, the severity and SoF of the circuit are evaluated with the amplitude and frequency margins characteristic of the IC outputs.

5.1 EMC model of the circuit under study

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