GENERATE instruction
VHDL-AMS Power Electronics and VHDL-AMS language -Methodological Contribution

The VHDL-AMS designer can describe in his code the iterative or conditional generation of instructions that will be integrated at design time according to static or generic parameter values using the instruction. GENERATE INSTRUCTION. This instruction is recursive and nestable.

The following sequence will conditionally generate instructions:

If generic_boolean_cond GENERATE

[Local declaration area

begin]

{instruction}

End ;

The next instruction will generate a certain number of instructions. This number will only be known at the time of processing:

For I in generic_range GENERATE

{instruction_i_dependant}

End ;

The following...