Appendix: CMOS technology

7. Appendix: CMOS technology

Figure 38 shows several views of the Metal Oxide Semiconductor (MOS) transistor: a spatial view (a ), a cross-sectional view (b ) and a top view (c ). Designers use the top view to draw the technological masks for fabrication. The transistor has two geometric parameters: its width W and its length L. The gate used to be made of metal (hence the name MOS). Today, it's made of polysilicon (heavily doped polycrystalline silicon).

The conductance between the drain and source regions is modulated by the voltage applied to the gate, which generates an electric field that modulates the number of carriers in the channel (field effect). MOS logic circuits have a minimum gate length to reduce the transit time of carriers...

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Appendix: CMOS technology