5. SIMD/vector register size and memory system

5.1 AVX-512

The AVX-512 instructions VMOVDQA, VMOVAPS, VMOVAPD for aligned loads and stores, and the equivalent instructions for non-aligned accesses, transfer 512 bits between the SIMD registers and the L1 data cache. Intel CPUs with the AVX-512 extension have cache lines of 64 bytes (512 bits). A CPU-to-L1 cache transfer therefore transfers an entire line. This means that the use of prefetch (hardware, or hardware plus software) is essential to avoid a cache miss on each access. The L1D...