Evolution of semiconductor random access memories

Since Intel's first static and dynamic random access memories appeared in 1969 and 1971 respectively, these components have continued to evolve in terms of storage capacity and performance, mainly latency and throughput. Dynamic memory capacity has thus increased from 1 Kib (Intel reference 1103 – 1971) to 32 Gib (DDR4 SDRAM – 2019), and its cycle time started at 580 ns to reach around 32.5 ns (DDR4-3200-20-32 line enabled model) for random reading (same references as above).

The aim of this article is to retrace the technical evolution of solid-state memory. The various sub-assemblies of this component - the memory matrix, the peripheral control logic and the interface - are first presented, followed by details of their development. Since the mid-1990s, advances in integration have made it possible to integrate a computer system on a single chip. We describe the advantages of embedded memory. Finally, we sketch out what the "ideal memory" would be, based on current research. It could have the same storage capacity as "conventional" memories, no volatility of information, a throughput compatible with current processor architectures, and greater energy efficiency. In particular, we present three current industrial solutions: phase-change, ferroelectric and magnetoresistive memories, represented respectively by PCRAM, ReRAM, FRAM and MRAM.

At the end of the article, readers will find a glossary and a table of acronyms and notations.