Manycore processors

Without taking into account graphics processing units (GPUs), which constitute a separate class of architecture, processors with a large number of cores differ from multicore processors not only in the number of cores, but also in a number of characteristics: the type and performance of the cores, the hierarchical breakdown into clusters (or nodes) of cores, the memory model (shared memory or distributed memory), and software issues related to the fact that they are almost always used as coprocessors. These manycores are used in three main classes of applications:

1. high-performance mobile and embedded applications for which energy constraints are fundamental;

2. applications for which high performance is the most important criterion, such as scientific computing;

3. specialized circuits for learning and inference in deep neural networks. This class of applications is the one that sees the largest number of circuits appearing.

The different characteristics are presented along with the different variants. Six examples of manycore processors are then described in detail.

The first two are architectures designed for high-performance mobile and embedded applications and dissipate between a few watts and thirty watts:

• processors implementing Adapteva's Epiphany architecture, with two versions used with 16 or 64 cores and a 1024-core version that was a failure;

• Kalray's MPPA architecture, including the study of MMPA2 and MPPA3 versions.

The following two examples are intended for high-performance computing and dissipate two to three hundred watts:

• Intel's Xeon Phi processors and coprocessors with the Knights Corner and Knights Landing models. Their production was discontinued in 2018;

• The SW26010 manycore processor used in the Chinese TaihuLight supercomputer, which ranked first in the TOP500 list of supercomputers from June 2016 to November 2017.

The last two examples correspond to the acceleration of learning and inference in neural networks:

• Untether's Boqueria AI accelerator consists of a 2D grid of memory blocks, which themselves consist of a 2D grid of blocks with an elementary processor and SRAM memory.

• Celebras' WSE-2 circuit interconnects a 2D grid of cores at the wafer level. Each core contains a computing section and an SRAM. With 850,000 cores and 15 kW of power dissipation, it is the largest circuit in 2022.