VHDL-AMS language

The VHDL-AMS language can be used to describe the behavior or structure of a system combining different operating paradigms interacting at different levels of abstraction. It is one of the designer's tools, assisting him at every stage of the technical design of a system, whatever its size or complexity. Its qualities of formalization, its ability to handle different levels of abstraction, its ability to mix technical disciplines, its integration into general CAD/CAM tools and the fact that it is based on a standard issued by the IEEE international association make it a highly effective tool for the designer in a company extended to all its collaborators (principals, partners, subcontractors, suppliers, etc.).

The VHDL-AMS hardware description language is a rich and relatively complex language. Like any language, it has a syntax and one or more semantics, i.e. it...