Analog-to-digital and digital-to-analog conversion (part 2)

The symmetry that exists between analog-to-digital (AD) and digital-to-analog (DA) conversion, when real number to binary code truncation is taken into account for DA conversion, partially disappears in converter architectures [except for Sigma-Delta (ΣΔ)].

AN converters are always more difficult to build than NA converters. DACs are comparatively easier to build, and for the same technology, DACs are an order of magnitude faster.

Numerous architectures have been invented to achieve the best possible AN conversion. These solutions have evolved along with the technologies used to achieve the best compromise between function, cost and performance. Many ADCs contain one or more feedback DACs (SAR, subranging, ΣΔ...).

One of the most frequently encountered criteria for comparing these converters is the figure of merit, which is the product of 2 to the power of the (effective) number of bits multiplied by the sampling frequency divided by the power consumption (see ) : $\text{Facteur de mérite}=2^{N_{\text{eff }}}\times f_{\text{éch }}\text{/}{P}_{\text{consommée }}$