Conclusion

The operation of the MOS transistor was described with a focus on its conventional (bulk) architecture. A description and model of its ideal theoretical behavior were first presented. These were then expanded to include parasitic effects, some of which become dominant as device dimensions shrink. The technological solutions implemented were then presented, along with the evolution of the associated performance metrics, which are essential for accurately capturing the effectiveness of technological optimizations.

Despite numerous technological improvements, conventional MOS transistor architecture has reached its limits at the 20-nm node, and the industry has decided to turn to other architectures to keep Moore’s Law alive: FD-SOI and multi-gate architectures.

Some manufacturers then chose to continue with FD-SOI architecture, which has the...