CMOS technologies - MOS transistor

Since Intel released the first integrated circuit (the Intel 4004) in 1971, silicon CMOS (Complementary Metal-Oxide Semiconductor) technologies have been continuously optimized to deliver higher performance and greater density: maximizing speed, minimizing power consumption, while reducing the area occupied by each transistor. The trade-off to be optimized is now broader and also takes environmental impact into account: today we refer to PPACE, which stands for Power, Performance, Area, Cost, and Environment. For example, between 1971 and 2012 (from the Intel 4004 to the Intel Core i7), integration density increased by a factor of 40,000 and speed by a factor of 27,000. The main objective of this article is to describe and explain how to quantify integration density, how to evaluate and optimize the performance of a MOS transistor, and its relationship to the performance of a digital integrated circuit.

Starting with a description of basic concepts, the various operating modes of the simplified silicon device will be described through the variation of the MOS capacitance as a function of voltage, in order to define the concept of threshold voltage—the boundary value between the transistor’s on and off states (ON and OFF). The operation of the MOS transistor will then be explained, starting from the ideal case and progressing to the ultimate transistor, relying as much as possible on simple equations, which are not intended to be precise but rather to illustrate and weigh the influence of the various parameters. The reduction in transistor dimensions, their impact on behavior and performance, the associated limitations, and the solutions implemented to continue miniaturization while improving performance will be explained. Evolutions in architecture and design rules require the establishment of new figures of merit and performance metrics, each of which will be detailed and justified. Throughout this article, the links between transistor performance and circuit performance on the one hand, and transistor behavior and technological solutions on the other, will be explained as much as possible. The specific features of CMOS technology fabrication will also be addressed: offering different devices using a single integration process. Finally, the need to turn to new MOS transistor architectures will be discussed: this is the turning point taken by the microelectronics industry in the 2010s to continue following Moore’s Law.