From planar MOSFET to multi-gate and 3D architectures

Fully Depleted SOI Devices: More Moore applications and New Architectures

Figure 1 - Complementary
Metal Oxide Semiconductor (CMOS) components made with FDSOI technology
and controlled by front and back gates

Figure 2 - Comparison
of carrier mobilities for Si and the alternative channels Ge and III-V

Figure 3 - Simulated
channel and buried oxide thicknesses for controlling DIBL short channel
effects of 100 mV.V−1 depending on channel length

Figure 4 - Impact
of doping fluctuation on threshold voltage variations of different
device architectures

Figure 5 - Impact
of tensile strain (obtained by the smart-cut process from Si/Si0.8 Ge0.2 relaxed layers) on very short FDSOI MOSFETs
with very thin films

Figure 6 - Double
gate MOS Transistor

Figure 7 - Gate-all-around
transistor

Figure 8 - Threshold
voltage reduction by DIBL effect for a double gate transistor with
respect to a single gate transistor

Figure 9 - Drain
current and transconductance of a transistor of thickness 3

Figure 10 - Quantum distribution of minority
carriers and electric field of a 3 nm SOI film MOSFET in DG and SG
modes (Vgs − Vt &#61; 2 V)

Figure 11 - Triple gate FinFET with multiple fins

Figure 12 - Quantum simulation comparison of subthreshold swing for Sub-10 nm
Ultimate Gate Lengths

Figure 13 - Multigate and multichannel MOSFETs with high drain currents at ON
state and low drain currents at OFF state

Figure 14 - Double gate transistor (TFET) with tunnel conduction between source/channel
and drain

Figure 15 - Drain currents for TFETs fabricated on SOI, SiGe/OI et Ge/OI

Figure 16 - Low inversion SS slope as a function of the InAs GAA nanowire diameter
and gate length for a supply voltage VDD &#61; 0.3 V

Figure 17 - Ion and subthreshold
swing for different nanowire architectures (d &#61; 5 mm, Lg &#61; 17 nm, Ion at Ioff &#61; 5 nA.µm−1)

Figure 18 - Double gate MOSFET compared to single gate MOSFET on 2D and UTB layers

Figure 19 - Double gate TFET on WTe2 layer with transfer characteristic ID (VG) as
a function of gate length (VD &#61; 0.5 V, S/D doping :
1013 cm−2)

Figure 20 - Hybrid component combining a TFET and a ferroelectric gate to improve
the electrical properties of the transistor

Figure 21 - Comparison of a FinFET and a ferroelectric gate hybrid FinFET (Hf0,42 Zr0,58 O2) allowing to go below
the 60 mV/decade limit

Figure 22 - FET tunnel with phase change VO2 material in the gate
showing an insulating-metal transition by electrical excitation