Conclusion

Given the stakes involved, it is no longer possible for companies designing complex integrated circuits to carry out validation dead-ends, without exposing themselves to very high risks. Validation is becoming more and more critical, and in order to reduce these risks as much as possible, highly sophisticated methodologies are being implemented. They are based on increasingly diversified tools, such as rule checkers, formal proofs, assertion languages, as well as reuse methods, such as for test programs, and efficiency measurement methods, such as coverage rate. Despite all this enrichment, the heart of validation remains simulation. Users will need to organize validation plans with ever greater care, but they will also need to optimize simulations by making the right choice of simulators in relation to validation criteria. Certainly, to keep pace with the needs of the most advanced silicon...