Acronyms

CMOS Integrated Circuits on Silicon

Figure 1 - Evolution of CMOS technology nodes

Figure 2 - The two CMOS technologies

Figure 3 - Determining the threshold voltage

Figure 4 - Principle for extracting parameters RT (parasitic resistances) and L

Figure 5 - Illustration of the impact of gate edge roughness on a FinFET transistor.

Figure 6 - Locking in a CMOS circuit

Figure 7 - Protection circuit

Figure 8 - Inverter symbol and design in CMOS technologies

Figure 9 - Examples of FDSOI and FinFET inverter designs

Figure 10 - Inverter transfer curves

Figure 11 - Total output load capacity of a CMOS inverter

Figure 12 - CMOS inverter output capacitance loading and unloading process

Figure 13 - Ring oscillator

Figure 14 - CMOS transmission port

Figure 15 - Dual-input NAND gate

Figure 16 - Drawing of a two-input NAND gate

Figure 17 - Two-input NOR gate in CMOS design

Figure 18 - Drawing of a NOR door with two entrances

Figure 19 - Dual-input XOR gate in CMOS technology

Figure 20 - Front-end design flow

Figure 21 - Illustration of a power mode description using the UPF file

Figure 22 - Examples of different floorplans for a circuit with five partitions

Figure 23 - Example of feeder grid with stud ring

Figure 24 - Example of how to place standard cells on the appropriate lines

Figure 25 - Examples of classically verified rules (from [1])

Figure 26 - Moore&#039;s Law from its beginnings to 2005 (according to [1])

Figure 27 - Grid lengths and metal pitches for nodes since 1995 and ITRS forecasts to 2028 (from [2])