From one to several instructions per cycle

The acceleration of processors has always been the main motivation of designers. Pipelined scalar processors aimed at an execution rate of one instruction per clock cycle (IPC = 1), using the techniques described in [H 1 004] . To execute several instructions of a sequential program per clock cycle (IPC > 1), two approaches are possible. The parallel execution of instructions is either controlled :

• by the hardware. Processors traditionally referred to as superscalar use this technique, either with "multi-pipeline" (in-order execution) or "restricted...