Digital phase-locked loop
Phase-locked loop

Schematic diagram

The loop can be realized in digital form by sampling the input signal at frequency f_e = 1/T. One embodiment is shown in figure 13.

The input signal sampled at frequency 1/T is applied to one of the inputs of the phase comparator realized in this case by a multiplier followed by a low-pass filter (in some cases, low-pass filtering is realized by the loop filter), the other input being attacked by the cos sequence (Ψ_s [k ]) from a digital controlled oscillator (DCO). The digital controlled oscillator is controlled by the output signal u₂ [k ] of a digital loop filter driven by u₁ [k ].