Partially depleted transistors
Silicon-on-insulator technology

In the case of partially depleted MOS/SOI transistors, the depletion charge controlled by one or two gates does not extend from one interface to the other. A neutral region remains and, consequently, interface coupling effects are suppressed. When the silicon layer is grounded (via independent contacts on the silicon film or direct source/film connections), partially depleted SOI devices behave similarly to those fabricated on bulk silicon. Most of the I_DS equations (V_GS, V_DS) and conventional architecture concepts can be applied. If body contacts are not available, so-called floating-substrate effects occur, leading to several major drawbacks which are explained below.