Multi-pipelines in scalar processors

For the single-cycle computation instructions of scalar processors, the operation box (UAL) is available at every clock cycle, as it uses only one cycle per operation for an instruction on integer data. On the other hand, there are no data dependencies, thanks to short-circuiting techniques that allow the output of the UAL to be fed back to one of its inputs.

Problems exist for load instructions and sequence-breaking instructions (jumps and branches). For the simple pipeline (figure 3 ), solutions exist to limit their impact. Compilers can mask the latency of load instructions. A debatable solution (delayed branching) and a good solution (branch address caches) can limit the impact of control instructions on performance (see