Article | REF: H1010 V1

Multi-pipeline superscalar processors

Authors: Daniel ETIEMBLE, François ANCEAU

Publication date: August 10, 2015, Review date: August 3, 2022 | Lire en français

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    6. Concluding remarks

    The common principle of multi-pipelines is to acquire a fixed number of instructions stored in a buffer, and to start these instructions in order when structural conflicts and data dependencies are resolved. Start conditions can be more or less strict, strictly limited to one group (21064 and 21164), extended to two groups (R8000) or facilitated by pre-processing at instruction decoding level (Power 6).

    In this approach, the limit to the exploitation of instruction parallelism existing in a sequential program is the number of candidate instructions to constitute the group of executable instructions for a given cycle. This number is low, since the groups are formed in sequence and execute in sequence. However, the instructions executable at a given time may be much further apart in the sequential program than the distance between the first and last instruction in...

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