Processors : pipelined execution of instructions

The aim of this article is to present the essential characteristics of pipelined instruction execution in processors, which is the simplest performance enhancement technique employed since the late 1950s by allowing a new instruction to begin execution while previous ones are still running. This overlapping in time of the execution of several instructions has evolved over time: early machines such as the IBM 360/91 and Intel processors up to the 80 386 used a "loose" pipeline. With the advent of RISC technology in the 1980s, processor pipelines became "tight", the notions of "loose" and "tight" being specified in the article.

Pipeline processing of simple instructions, those whose operations in the computing unit are executed in one clock cycle, is examined in detail. The MIPS R2000 pipeline is used as an example, showing how instructions are broken down into elementary steps and executed by the hardware. The treatment of data dependencies and control dependencies is explained, including the problem of branches and interrupts. The pipeline of a CISC processor, the Intel i486, is also discussed.

Multiplication and division operations on integer data and all floating-point operations cannot be executed within the clock cycle of simple arithmetic and logic operations. This complicates pipelined instruction processing by introducing more complex data dependencies: true dependencies, antidependencies and output dependencies. Techniques for controlling true dependencies are presented. While they guarantee correct operation, they can introduce suspensions. Software techniques such as loop unwinding or software pipelining can reduce or eliminate these suspensions. Antidependencies and output dependencies can be eliminated by register renaming. The problem of unordered instruction termination is also addressed.

To improve performance, pipelining was the preferred technique for high-end processors until the mid-1990s. It remains the preferred technique for processors used in embedded and buried applications, where the – silicon area – energy trade-off is more important than performance alone. It has only shown its full potential with the emergence of new techniques, such as "data flow" execution of classic sequential code, or VLIW execution, which make better use of the instruction parallelism existing in classic sequential code.