3. Material problems accentuated

3.1 Register banks

In the simple pipeline shown in figure 3 (scalar case), an instruction in the DI/LR phase can read the contents of two registers, and another can write in the ER phase to another register. The problem of simultaneous reading and writing to the same register can be solved in two ways:

• 1) if the clock period is at least double the read or write time, write in the first half-cycle and read in the second half-cycle;

• 2) otherwise, read operations are delayed by one cycle....