Pipeline execution of simple instructions
Processors : pipelined execution of instructions
Article REF: H1004 V1
Pipeline execution of simple instructions
Processors : pipelined execution of instructions

Authors : Daniel ETIEMBLE, François ANCEAU

Publication date: August 10, 2013, Review date: March 4, 2022 | Lire en français

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2. Pipeline execution of simple instructions

2.1 Steps in instruction execution

In the appendix paragraph of the article Introduction to computer architecture [H 1 000] , the non-pipelined execution of the instructions of a small machine, with the different stages, is as follows:

  • reading the instruction (LI) ;

  • update program counter (CP) ;

  • instruction decoding (DI) ;

  • reading operands...

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