Problems related to instructions with multi-cycle operations
Processors : pipelined execution of instructions
Article REF: H1004 V1
Problems related to instructions with multi-cycle operations
Processors : pipelined execution of instructions

Authors : Daniel ETIEMBLE, François ANCEAU

Publication date: August 10, 2013, Review date: March 4, 2022 | Lire en français

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3. Problems related to instructions with multi-cycle operations

3.1 Multi-cycle operations

All the operations performed in the ALU considered so far are executed in one clock cycle. Logical instructions work on a bit-by-bit basis and have no carry to propagate. Simple arithmetic operations on integer data (addition and subtraction) can be executed in one clock cycle. On the other hand, multiplication and division operations on integer data are long operations, requiring several clock cycles. There are two ways of performing a hardware multiplication.

The first consists of a sequence of additions and shifts controlled by a sequencer, each step requiring one clock cycle. This approach, with possible variants allowing several multiplier bits to be processed at once to reduce the number of iterations, was used in early processors...

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