From one instruction to several instructions per cycle
Out-of-order superscalar processors
Article REF: H1011 V1
From one instruction to several instructions per cycle
Out-of-order superscalar processors

Authors : François ANCEAU, Daniel ETIEMBLE

Publication date: January 10, 2018, Review date: August 3, 2022 | Lire en français

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1. From one instruction to several instructions per cycle

The acceleration of processors has always been the main motivation of designers. Pipelined scalar processors aimed to achieve an execution rate of one instruction per clock cycle (IPC = 1), using the techniques described in the article [H 1 004] . To execute several instructions of a sequential program per clock cycle (IPC > 1), two approaches are possible: the VLIW approach

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