DSP memory architecture
Digital Signal Processors (DSP)
Archive REF: E3565 V1
DSP memory architecture
Digital Signal Processors (DSP)

Authors : Gérard BLANCHET, Patrick DEVRIENDT

Publication date: February 10, 2000 | Lire en français

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2. DSP memory architecture

It's a commonplace to say that memory is "the" bottleneck in processor operation. Many tricks can be used to achieve a throughput compatible with the processor's speed: caches, organization into banks and burst access, multi-access memory, etc. [2] .

.Simplified diagram of the TMS32010 memory architecture
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