Fully Depleted SOI Devices: More Moore applications and New Architectures

The historical trend in micro/nanoelectronics over the last forty years has been to increase the speed and density of integration by reducing the size of electronic devices, by reducing the energy dissipation for logical applications and developing many new functionalities for future electronic systems. We face substantial challenges if we are to continue this exponential growth in performance : substantial increase in power consumption and circuit heating that can compromise the future integration and performance of integrated circuits, reduced performance of traditional low-permittivity metal/dielectric interconnects, lithography, heterogeneous integration of new functionalities for future nanosystems, etc.

As a result, many breakthrough technologies, new materials and innovative devices are needed today. With regard to the increase in performance and the substantial reduction in the static and dynamic power of high performance and ultra low power logic circuits, as well as autonomous nanosystems, which is the subject of this article, alternative materials and/or new device architectures are required for CMOS and beyond-CMOS technologies.

This article focuses on the main trends, challenges, limitations and possible solutions for highly integrated devices based on FD Silicon On Insulator technology, as well as its extensions to push the limits of circuit integration and optimize their performance. We will deal with the most mature or promising technologies : FDSOI MOS devices including possible performance accelerators (alternative Ge and III-V channels, effects of mechanical strain, control of short channel phenomena and variability of electrical properties), evolution of FDSOI devices to innovative architectures (double-gate, triple-gate/FinFET, gate-all-around, 3D integration), emerging components in FDSOI (tunnel FET with low subthreshold swing), quasi-SOI FET(MOSFET and TFET on 2D layer on insulator) and hybrid devices (MOSFET and TFET with ferroelectric gate, MOSFET and TFET integrating innovative phase change or nanofilament-based materials).

At the end of the article, the reader will find a glossary of important terms and expressions in this article, along with a table of signs, notations and symbols used throughout the article.