Fully Depleted Silicon On Insulator (FD-SOI) Devices

SOI technology, the subject of the article "Silicon-on-insulator (SOI) technology". [E 2 380] has given rise to FD-SOI, a cutting-edge CMOS process in which fully depleted (FD) components are only 6 to 7 nm thick. This article discusses, in some detail, the specific features of FD-SOI compared with conventional, thicker SOI structures.

The emphasis is on the incomparable flexibility of FD-SOI compared with its competitor, FinFET. The ability to bias the silicon substrate is the undisputed strength of FD-SOI, enabling the emulation of dual-gate transistors. This allows us to modulate transistor properties in terms of threshold voltage, carrier mobility and leakage current.

First, the generic advantages and characteristics of FD-SOI components are described. We then explain the specific physical mechanisms governing the operation of MOSFET transistors. Emphasis is placed on dimensional effects in terms of channel thickness and length. The characterization of multi-interface structures of nanometric size represents a considerable challenge. Recommended techniques are then discussed. The extreme flexibility of the technology offers the opportunity to design innovative devices, essentially based on the exploitation of electrostatic doping. Selected examples are discussed: band-modulated devices, virtual diodes, DRAM memories without storage capacity, etc.

For a complete and synthetic view, it's best to browse this article after reading the [E 2 380] article.

At the end of the article, readers will find a table of symbols and a table of acronyms used.