MMIC technologies

MMIC :Advanced and technology

Figure 1 - Noise factor as a function of frequency for LNA MMIC technology channels

Figure 2 - Output powers as a function of frequency for PA MMIC technology chains

Figure 3 - IC design flow.

Figure 4 - Architectural simulation

Figure 6 - VCO time output (simulation result)

Figure 7 - Transmitter output spectrum (simulation result)

Figure 9 - RF SOC floorplan circuit diagram

Figure 10 - Grid deposit

Figure 11 - Two processes for obtaining a metal or dielectric layer

Figure 12 - Example of air bridge technology

Figure 13 - Sequence of main operations for PHEMT technology on GaAs

Figure 14 - Sequence of the main operations of a CMOS technology (example of the 65 nm node) and specific operations of the corresponding BiCMOS technology.

Figure 15 - Interconnections between BiCMOS technology optimized for millimeter-scale applications (BiCMOS9MW) and 0.13 μm CMOS technology (HCMOS9 and HCMOS9SOI) and BiCMOS (BiCMOS9)

Figure 17 - Quality factor of a 0.5 nH inductor realized with metal levels 5, 6 and aluminum for BiCMOS9 and BiCMOS9MW technologies

Figure 18 - Photo of a cutting path in silicon technology