6. Caches and user programs

The structure and hardware organization of processors' internal caches are the responsibility of the processors' designers. Only marginally, and for configurable processors or processors integrated in FPGAs (Field Programmable Gate Arrays), can the designer of a hardware system define the characteristics of the caches used.

As the part of the memory hierarchy made up of cache levels and main memory is managed by the hardware, the cache hierarchy is "transparent" to the user and he can ignore it: however he writes a program in a high-level language, if the written program is correct, after compilation, it will execute correctly. When it comes to execution time, the situation is completely different. A program written in a high-level language can have very different execution times, depending on the choice of data structure, the order of loops in loop nests... A compiler...