Symmetrical multiprocessor caches
Memory hierarchy: caches
Article REF: H1002 V1
Symmetrical multiprocessor caches
Memory hierarchy: caches

Authors : Daniel ETIEMBLE, François ANCEAU

Publication date: August 10, 2012, Review date: March 8, 2022 | Lire en français

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3. Symmetrical multiprocessor caches

SMP symmetrical multiprocessors are parallel architectures with several processors, each with its own cache hierarchy, and a logically shared main memory, i.e. the same address space is visible to all processors. This logically shared memory can be physically shared (a single main memory) or physically distributed (each processor has its own local memory, but a single address space).

.Illustration of the coherence problem
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