Techniques to limit the impact of caches
Memory hierarchy: caches
Article REF: H1002 V1
Techniques to limit the impact of caches
Memory hierarchy: caches

Authors : Daniel ETIEMBLE, François ANCEAU

Publication date: August 10, 2012, Review date: March 8, 2022 | Lire en français

Logo Techniques de l'Ingenieur You do not have access to this resource.
Request your free trial access! Free trial

Already subscribed?

4. Techniques to limit the impact of caches

4.1 Preloading

One way of limiting the impact of caches on performance is to avoid cache misses by causing the necessary cache lines to be preloaded before executing the instruction that would cause the cache miss. This preloading can be done in hardware or by executing preloading instructions in software.

SCROLL TO TOP

4.1.1 Material preloading

Loading instruction or data lines into the respective caches in advance poses a number of problems:

  • which line should...

You do not have access to this resource.
Logo Techniques de l'Ingenieur

Exclusive to subscribers. 97% yet to be discovered!

You do not have access to this resource. Click here to request your free trial access!

Already subscribed?


Article included in this offer

"Software technologies and System architectures"

( 227 articles )

Complete knowledge base

Updated and enriched with articles validated by our scientific committees

Services

A set of exclusive tools to complement the resources

View offer details