4. Integrating low-energy techniques into the design flow

Commercial circuit simulation and synthesis tools offer functions for integrating power management mechanisms into a circuit. Some power consumption optimization techniques are directly integrated into logic synthesis tools, for example the use of flip-flops where the clock can be controlled by an authorization signal to perform local clock gating. On the other hand, structuring an RTL model of a circuit architecture to include power management mechanisms such as those described above is a function of more general-purpose tools.

As a result, CAD tool vendors have been offering low-power extensions to their classic design flow, based on a textual specification of a power management structure (often called a power intent). The first formalisms introduced to describe a power intent date back to 2005; since then, the IEEE 1301 Unified Power Format (UPF) standard has...